There is developed a semiconductor device in which semiconductor chips are stacked for a purpose of reducing a package density. A CoC (Chip on Chip) technology, in which a semiconductor chip is flip-chip bonded onto another semiconductor chip, is used for the purpose of reducing the package density. The flip-chip-bonding is hereinafter referred to as FCB. Au (gold), Cu (copper), solder or the like is used as a bump for the FCB.
FIG. 1 illustrates a cross sectional view of a semiconductor device in accordance with a first conventional embodiment. A first semiconductor chip 11 is face-up mounted on an intermediate substrate 50 through a die attach member 88. A wiring 12 is provided on the first semiconductor chip 11. A second semiconductor chip 20 is flip-chip bonded onto a pad 12a of the wiring 12 through a bump 14. A first resin member 86 acting as an under fill member is formed between a bottom face of the second semiconductor chip 20 (a face on which a circuit is formed) and an upper face of the first semiconductor chip 11 (a face on which a circuit is formed). The first semiconductor chip 11 and the second semiconductor chip 20 are sealed with a second resin portion 80. A wiring 52 for a redistribution pattern or a flip-chip pad is provided on an upper face of the intermediate substrate 50. A wiring 54 for a land electrode is provided on a bottom face of the intermediate substrate 50. The wiring 52 and the wiring 54 are electrically coupled to each other with a coupling portion 56. A solder ball 58 is formed on the wiring 54. The first semiconductor chip 11 and the wiring 52 of the intermediate substrate 50 are electrically coupled to each other through a bonding wire 82.
FIG. 2 illustrates a cross sectional view of a semiconductor device in accordance with a second conventional embodiment. The first semiconductor chip 11 is flip-chip bonded onto the intermediate substrate 50. The second semiconductor chip 20 is face-up mounted on the first semiconductor chip through the die attach member 88. An upper face of the second semiconductor chip 20 is electrically coupled to the wiring 52 of the intermediate substrate 50 through the bonding wire 82. Other structure is the same as that of the first conventional embodiment. And an explanation is omitted.
Japanese Patent Application Publication No. 2000-156461 (hereinafter referred to as Document 1) discloses a third conventional embodiment where a semiconductor chip and a solder ball interposer are flip-chip bonded onto a semiconductor wafer, a resin is coated, and the resin is grinded.
In the first conventional embodiment and the second conventional embodiment, a packaging density is reduced because the first semiconductor chip 11 and the second semiconductor chip 20 are stacked. However, either the first semiconductor chip 11 or the second semiconductor chip 20 is flip-chip bonded. There is a problem that it is difficult to reduce a thickness of a semiconductor chip to be flip-chip bonded to less than 100 μm. This is because it is difficult to handle a thin semiconductor chip from a wafer or a chip tray when the semiconductor chip is flip-chip bonded. And this is because handling is difficult, an under fill member reaches an upper face of the semiconductor chip having a small thickness, and the under fill member is adhered to a bonding tool for handling the semiconductor chip, when the flip-chip bonding is preformed with Au—Au compression method. It is difficult to reduce the thickness of the semiconductor chip in the first conventional embodiment and the second conventional embodiment where the semiconductor chip is flip-chip bonded.
In FIG. 12 in Document 1, thickness of a semiconductor chip 130 is not reduced, although a coated layer is grinded. And it is difficult to reduce the thickness of the semiconductor device.
An under fill member is provided in order to restrain an electrical short caused by a foreign material or the like, when the semiconductor chip is flip-chip bonded. However, a manufacturing cost is increased because the under fill member is provided in each of the semiconductor chips.